This book is written for both experienced users and beginners, and covers Verilog HDL extensively.
It covers a wide range of practical design and synthesis of Verilog, not just from a programming language perspective.
Additionally, the information covered in this book is fully compliant with the IEEE 1364-2001 Verilog HDL standard.

This edition:
? Explains the latest verification technologies.
? It covers gate, RTL, behavioral and switch level modeling.
? Introducing the PLI (Programming Language Interface).
? It describes the logic synthesis methodology.
? Explains timing and delay simulation.
? Explains about user-defined primitives.
? It provides many practical modeling techniques.

This book provides over 300 illustrations, examples, exercises, and a list of Verilog resources.
Each chapter provides learning objectives and a summary.

“Mr. Palnitkar shows why and how Verilog HDL is used for most complex circuit designs today.
This book will be a valuable reference for beginners as well as experienced Verilog users.
I highly recommend this book to anyone doing Verilog-based designs.”
-Rajeev Madhavan, Chairman and CEO of Magma Design Automation

"This book is unique in the breadth of information it provides when it comes to covering Verilog and Verilog-related topics.
It provides readers with the basic information they need, aligned with the IEEE 1364-2001 standard, and includes several chapters covering advanced topics in verification, PLI, synthesis, and modeling techniques.
-Michael Mcnamara, IEEE 1364-2001 Verilog Standards Association Chair

"This is a book I often use when teaching at universities.
This is the only book that covers practical Verilog.
A must-read for beginners and experts alike.
-Berend Ozceri, Design Engineer, Cicso Systems, Inc.

“The simplicity, logic, and meticulous composition hidden within the rich illustrations make this book an ideal textbook.”
-Arun K.
Somani, Professor Emeritus, Iowa State University